A conventional integrated circuit contains a plurality of patterns of metal lines separated by inter-wiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the metal patterns of vertically spaced metallization layers are electrically interconnected by vias. Metal lines formed in trench-like openings typically extend substantially parallel to the semiconductor substrate. Semiconductor devices of this type, according to current technology, may comprise eight or more levels of metallization to satisfy device geometry and micro miniaturization requirements.
A common method for forming metal lines is known as “damascene.” Generally, this process involves forming an opening in the dielectric interlayer, which separates the vertically spaced metallization layers. The opening is typically formed using conventional lithographic and etching techniques. After an opening is formed, the opening is filled with copper or copper alloys to form a metal line and/or a via. Excess metal material on the surface of the dielectric interlayer is then removed by chemical mechanical polishing (CMP). Although copper has low resistivity and high reliability, copper still suffers from electro-migration (EM) and stress-migration (SM) reliability issues as geometries continue to shrink and current densities increase. Various approaches are thus explored to solve these problems.
FIG. 1 illustrates a conventional interconnect structure. Two copper lines 2 and 4 are formed adjacent to each other and are insulated from low-k dielectric layer 14 by diffusion barrier layers 6 and 8, respectively. Metal caps 10 and 12, which are typically formed of materials suffering less from electro-migration, are formed on copper lines 2 and 4, respectively. The formation of metal caps greatly improves the reliability of the integrated circuit by reducing the surface migration of the copper lines. It has been found that under stressed conditions, the mean time to failure (MTTF) of the illustrated interconnection structure may be ten times longer than that of an interconnect structure having no metal caps. Part of the reason for the improvement is the reduction of electro-migration. With the metal caps, stress-induced void formation is also significantly reduced.
The introduction of metal caps generates another problem, however. Metal caps are typically formed on copper lines, thus increasing the height of the conductive materials. In the illustrated example, the formation of metal caps 10 and 12 increases the height of the conductive materials from H to H′. The parasitic capacitance between copper lines 2 and 4 (as well as the conductive materials surrounding copper lines 2 and 4) form a parasitic capacitor, and the capacitance is proportional to the cross-sectional area of lines 2 and 4. Therefore, the formation of metal caps 10 and 12 causes the parasitic capacitance to be H′/H times the capacitance as if no metal caps are formed, wherein the increase may be as much as five to ten percent. As a result, the RC delay of the integrated circuit is increased.
An additional effect caused by the formation of metal caps 10 and 12 is the increase in leakage current. Since metal caps 10 and 12 are selectively formed on copper lines 2 and 4, but not on low-k dielectric layer 14, any selectivity loss will cause metal to be formed on low-k dielectric layer 14. The leakage current between metal caps 10 and 12 is thus increased.
In order to reduce parasitic capacitances and leakage currents between neighboring conductive features, a new method of forming interconnection structures is needed.